4502 Datasheet, PDF (76/116 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4502 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag)
Instruction
code
D9
D0
Number of Number of Flag CY
0000101111
02F
words
cycles
2
16
1
1
–
Skip condition
(CY) = 0
Operation: (CY) = 0 ?
Grouping: Arithmetic operation
Description: Skips the next instruction when the con-
tents of carry flag CY is “0.”
After skipping, the CY flag remains un-
changed.
Executes the next instruction when the con-
tents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
D9
D0
Number of Number of Flag CY
0000100100
024
words
cycles
2
16
2
2
–
0 0 0 0 1 0 1 0 1 1 ₂ 0 2 B ₁₆
Skip condition
(D(Y)) = 0
(Y) = 0 to 5
Operation:
(D(Y)) = 0 ?
(Y) = 0 to 5
Grouping: Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
Note:
Set 0 to 5 to register Y because port D is six
ports (D0–D5). When values except above
are set to register Y, this instruction is
equivalent to the NOP instruction.
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
code
D9
D0
Number of Number of
1000110000
230
2
16
words
1
cycles
1
Flag CY
–
Skip condition
–
Operation:
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 re-
load register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction
code
D9
D0
Number of Number of
1
0
0
0
1
1
0
0
0
1
2
2
3
1 ₁₆
words
1
cycles
1
Flag CY
–
Skip condition
–
Operation:
(T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
Rev.3.01 2005.02.02 page 76 of 112
REJ03B0105-0301