4502 Datasheet, PDF (32/116 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4502 Group
Table 12 A/D control registers
A/D control register Q1
at reset : 00002
at RAM back-up : state retained
Q13 A/D operation mode selection bit
0
A/D conversion mode
1
Comparator mode
Q12 Not used
Q11
Analog input pin selection bits
Q10
0
1
Q11 Q10
00
01
10
11
This bit has no function, but read/write is enabled.
AIN0
AIN1
AIN2
AIN3
Selected pins
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
(1) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(2) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this reg-
ister can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute these instructions dur-
ing A/D conversion.
When the contents of register AD is n, the logic value of the com-
parison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following for-
mula:
Logic value of comparison voltage Vref
Vref = ^VDD ✕ n
1024
n: The value of register AD (n = 0 to 1023)
(6) Operation description
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4502 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D con-
version stops after 62 machine cycles (46.5 µs when f(XIN) = 4.0
MHz in high-speed mode) from the start, and the conversion result
is stored in the register AD. An A/D interrupt activated condition is
satisfied and the ADF flag is set to “1” as soon as A/D conversion
completes (Figure 29).
(3) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to “1” when A/D con-
version completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(4) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(5) A/D control register Q1
Register Q1 is used to select the operation mode and one of ana-
log input pins.
Rev.3.01 2005.02.02 page 32 of 112
REJ03B0105-0301