4502 Datasheet, PDF (25/116 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4502 Group
Clock
XIN
generation
circuit
System clock
Instruction clock
W13
Division circuit ^{MR3, MR2}
divided by 8
11
0
10
divided by 4
01
Internal clock
generating circuit
1
divided by 2
00
(divided by 3)
Prescaler
W 12
1/4
0
1/16
1
P13/INT
I13
ORCLK
I12
Falling
0
One-sided edge ^I11
detection circuit
0
(Note 1)
W10
SQ
1
1
Both edges
1
Rising
detection circuit
0
R
I10
W22
Timer 1 underflow signal
(Note 2) W11
0
1
Timer 1 (8)
(TAB1)
Reload register R1 (8)
T1AB
(TR1AB)
T1AB
Register B Register A
(TAB1)
W21,W20
00
01
10
11
Timer 1 underflow signal
W23 (Note 2)
0
1
Timer 2 (8)
(TAB2)
Reload register R2 (8)
(T2AB)
Register B Register A
(TAB2)
Timer 1
T1F
interrupt
Timer 2
T2F _interrupt
P12/CNTR
W60
0
W61
P12 output
0
1
1
1/2
1/2
Timer 2 underflow signal
Instruction clock
16-bit timer (WDT)
1
16
WRST instruction
(Note 3)
SQ
WDF1
R
Reset signal
(Note 5)
DWDT instruction
+
WRST instruction
(Note 4)
SQ
WEF
R
DQ
WDF2
TR
Reset signal
Data is set automatically from each reload
register when timer 1 or 2 underflows
(auto-reload function)
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P13/INT pin selected by
bits 1 (I11) and 2 (I12) of register I1.
2: Count source is stopped by clearing to “0.”
3: When the WRST instruction is executed at
WDF1 flag = “1,” WDF1 flag is cleared to “0”
and the next instruction is skipped.
Watchdog
reset signal
When the WRST instruction is executed at
WDF1 flag = “0,” skip is not executed.
4: When the DWDT and WRST instructions are
executed continuously, WEF flag is cleared to
“0” and reset by watchdog timer is not executed.
5: The WEF flag is set to “1” at system reset or
RAM back-up mode.
Fig. 22 Timers structure
Rev.3.01 2005.02.02 page 25 of 112
REJ03B0105-0301