4502 Datasheet, PDF (48/116 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4502 Group
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁Register initial values 1
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial
values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accord-
ingly, be careful not to over the stack when performing these
operations together.
➄ Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
➅Timer count source
Stop timer 1 or 2 counting to change its count source.
➆ Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
➇Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB or T2AB
instruction to write its data.
➈Writing to reload register R1
When writing data to reload register R1 while timer 1 is operat-
ing, avoid a timing when timer 1 underflows.
10 _{Timer 1 and timer 2 count start timing and count time when}
operation starts
Count starts from the first rising edge of the count source (2) af-
ter timer 1 and timer 2 operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the
count source) than time among next underflow (4) by the timing
to start the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer 2, timer
2 operates synchronizing with the falling edge of CNTR input.
Count Source
Count Source
(CNTR input)
Timer Value
(2)
32 1 0 3 2 1 0 3 2
Timer Underflow
Signal
(3)
(4)
(1) Timer
Fig. 48 Timer count start timing and count time when opera-
tion starts (T1, T2)
11 _{Watchdog timer}
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
• The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction continu-
ously every system is returned from the RAM back-up, and stop
the watchdog timer function.
12 _{Multifunction}
• The input/output of D2, D3, P12 and P13 can be used even when
C, K, CNTR (input) and INT are selected.
• The input of P12 can be used even when CNTR (output) is selected.
• The input/output of P20, P21, P30 and P31 can be used even
when AIN0, AIN1, AIN2 and AIN3 are selected.
13 _{Program counter}
Make sure that the PCH does not specify after the last page of
the built-in ROM.
14 _{POF and POF2 instructions}
When the POF or POF2 instruction is executed continuously af-
ter the EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction and the POF or POF2
instruction continuously.
Rev.3.01 2005.02.02 page 48 of 112
REJ03B0105-0301