4502 Datasheet, PDF (105/116 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4502 Group
Recommended operating conditions 1
(Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
VRAM
RAM back-up voltage
VSS
Supply voltage
VIH
“H” level input voltage
VIH
“H” level input voltage
VIH
“H” level input voltage
VIH
“H” level input voltage
VIH
VIL
VIL
VIL
VIL
IOL(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
IOL(avg)
IOL(avg)
ΣIOL(avg)
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level total average current
Conditions
Min.
High-speed mode
f(XIN) ≤ 4.4 MHz
2.7
Middle-speed mode
(Note 1)
Low-speed mode
Default mode
(at RAM back-up mode with the POF2 1.8 (Note 2)
instruction)
P0, P1, P2, P3, D2, D3, XIN
D0, D1, D4, D5
RESET
C, K
VDD = 4.0 to 5.5 V
VDD = 2.7 to 5.5 V
CNTR, INT
P0, P1, P2, P3, D0–D5, XIN
C, K
RESET
CNTR, INT
P2, P3, RESET
VDD = 5.0 V
D0, D1
D2/C, D3/K, D4, D5
P0, P1
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
P2, P3, RESET (Note 3) VDD = 5.0 V
D0, D1 (Note 3)
VDD = 5.0 V
D2/C, D3/K, D4, D5 (Note 3) VDD = 5.0 V
P0, P1 (Note 3)
VDD = 5.0 V
P2, D, RESET
P0, P1, P3
0.8VDD
0.8VDD
0.85VDD
0.5VDD
0.7VDD
0.85VDD
0
0
0
0
Limits
Typ.
0
Unit
Max.
5.5
V
V
V
VDD
V
12
V
VDD
V
VDD
V
VDD
V
VDD
V
0.2VDD V
0.16VDD
0.3VDD V
0.15VDD
10
mA
40
mA
24
mA
24
mA
5.0 mA
30
mA
15
mA
12
mA
80
mA
80
mA
Notes 1: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less.
2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (system enters into the reset state when the value is
VRST or less). In the RAM back-up mode with the POF2 instruction, the voltage drop detection circuit stops.
3: The average output current (IOH, IOL) is the average value during 100 ms.
Ceramic resonator and high-speed mode selected
f [MHz]
VRST (Note)
External clock input (ceramic resonator selected)
f [MHz]
VRST (Note)
4.4
Recommended operating
condition
3.2
Recommended operating
condition
VDD[V]
2.7
4.2
5.5
VDD[V]
2.7
4.2
5.5
Note: It shows the electrical characteristics range of detected voltage
for voltage drop detection circuit.
System reset occurs when the supply voltage is under
the detected voltage for voltage drop detection circuit.
Rev.3.01 2005.02.02 page 105 of 112
REJ03B0105-0301