H8S-2633 Datasheet, PDF (759/1487 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.3 Operation
15.3.1 Watchdog Timer Operation
IT To use the WDT as a watchdog timer, set the WT/ bit in TCSR and TME bit to 1. Software
must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflows occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, in
WDTOVF WDTOVF the WDT0 the
signal is output. This is shown in figure 15.4 (a). This
signal
WDTOVF can be used to reset the system. The
signal is output for 132 states when RSTE = 1, and
for 130 states when RSTE = 0.
WDTOVF ^{If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2633}
Group internally is generated at the same time as the
signal. This reset can be selected
as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states.
RES If a reset caused by a signal input to the pin occurs at the same time as a reset caused by a
RES WDT overflow, the pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system
clock periods (516φ) (515 or 516 states when the clock source is φSUB (PSS = 1)). This is
illustrated in figure 15.4 (b).
An NMI request from the watchdog timer and an interrupt request from the NMI pin are both
treated as having the same vector. So, avoid handling an NMI request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 5.00 Mar 28, 2005 page 697 of 1422
REJ09B0234-0500