H8S-2633 Datasheet, PDF (189/1487 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)
Bit
:
7
—
Initial value :
0
R/W
:—
6
5
4
3
IPR6 IPR5 IPR4
—
1
1
1
0
R/W R/W R/W
—
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Register
6 to 4
IPRA
IRQ0
IPRB
IRQ2
IRQ3
IPRC
IRQ6
IRQ7
IPRD
IPRE
Watchdog timer 0
PC break^*
IPRF
TPU channel 0
IPRG
TPU channel 2
IPRH
IPRI
IPRJ
TPU channel 4
8-bit timer channel 0^*
DMAC^*
IPRK
IPRL
SCI channel 1
8-bit timer 2, 3^*
IPRO
SCI channel 3
Note: * This function is not available in the H8S/2695.
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC^*
Refresh timer^*
A/D converter, watchdog timer 1^*
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1^*
SCI channel 0
SCI channel 2
IIC (Option)^*
SCI channel 4
Rev. 5.00 Mar 28, 2005 page 127 of 1422
REJ09B0234-0500