H8S-2633 Datasheet, PDF (186/1487 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in Figure 5.1.
SYSCR
NMI input
IRQ input
INTM1, INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
Internal interrupt
request
SWDTEND to
TEI4
Interrupt controller
Priority
determination
IPR
CPU
Interrupt
request
Vector
number
I
I2 to I0
CCR
EXR
Legend:
ISCR: IRQ sense control register
IER: IRQ enable register
ISR: IRQ status register
IPR: Interrupt priority register
SYSCR: System control register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 5.00 Mar 28, 2005 page 124 of 1422
REJ09B0234-0500