H8S-2633 Datasheet, PDF (218/1487 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
5.6.2 Block Diagram
Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller.
DMAC*
Interrupt
request
IRQ
interrupt
Interrupt source
On-chip
clear signal
supporting
module
Selection
circuit
Select
signal
Clear signal
DTCER
DTVECR
SWDTE
clear signal
Control logic
Interrupt controller
Determination of
priority
DTC activation
request vector
number
Clear signal
CPU interrupt
request vector
number
I, I2 to I0
DTC*
CPU
Note: * This function is not available in the H8S/2695.
Figure 5.9 Interrupt Control for DTC* and DMAC*
Rev. 5.00 Mar 28, 2005 page 156 of 1422
REJ09B0234-0500