H8S-2633 Datasheet, PDF (1253/1487 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Appendix A Instruction Set
Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals
during execution of the above instruction with an 8-bit bus, using three-state access with no wait
states.
φ
Address bus
RD
HWR, LWR
High level
R:W 2nd
Fetching
3rd byte
of instruction
Fetching
4th byte
of instruction
Internal
operation
R:W EA
Fetching
1nd byte of
instruction at
jump address
Fetching
2nd byte of
instruction at
jump address
Figure A.1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
Rev. 5.00 Mar 28, 2005 page 1191 of 1422
REJ09B0234-0500