M66591GP Datasheet, PDF (69/133 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
2.38 PIPE i Control Register (i=1~4)
„ PIPE 1 Control Register (Pipe1Ctrl)
„ PIPE 2 Control Register (Pipe2Ctrl)
„ PIPE 3 Control Register (Pipe3Ctrl)
„ PIPE 4 Control Register (Pipe4Ctrl)
<Address: H’A0>
<Address: H’A2>
<Address: H’A4>
<Address: H’A6>
b15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 b0
BSTS
ACLR SQCLR
NYETMD
PID [1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
-
-
-
0
0
<H/W reset: H’0000>
<S/W reset: H’0000>
<USB bus reset: B’---- ---- ---- --00>
b
Bit name
Function
RW
15 BSTS
0: Disables to read the data of buffer and to write the data to { -
Buffer Status
buffer
1: Enables to read the data of buffer and to write the data to
buffer
14~10 Reserved. Set it to “0”.
“0” “0”
9 ACLR
• Write
{{
Buffer Automatic Clear Mode
0: Disable buffer automatic clear
1: Enable buffer automatic clear
8 SQCLR
• Write
“0” {
Sequence Bit Clear
0: Invalid
1: Sequence bit clear
7~5 Reserved. Set it to “0”.
“0” “0”
4 NYETMD
0: Automatic response mode
{{
NYET Handshake Mode
(ACK/NYET is automatically selected.)
1: ACK response only mode
(Always with ACK response. No NYET response.)
3~2 Reserved. Set it to “0”.
“0” “0”
1~0 PID [1:0]
00: NAK response
{{
Response PID
01: BUF response
1x: STALL response
(1) BSTS (Buffer Status) Bit (b15)
This bit indicates the buffer status of PIPE1 to PIPE4.
(2) ACLR (Buffer Automatic Clear Mode) Bit (b9)
When this bit is set to “1”, all the buffers on the CPU-side/SIE-side are cleared.
This bit is not automatically cleared to “0” on completion of buffer clear, make sure to write “0” after setting “1”.
When the PID [1:0] bits are set to “01” (BUF) during setting the OUT buffer and this bit to “1”, the NAK response
are not executed in the received OUT token. The ACK response is returned to the host after the data being received.
At this time, this received data are not written to the buffer. Also, when the PID [1:0] bits have been sets to “00”/”1x”
(NAK/STALL), the NAK/STALL response is executed.
Only the SIE-side buffers and the write completion CPU-side buffer are cleared by setting “1” to this bit during
setting the IN buffer. To clear the SIE-side buffers, follow the procedure below.
(1) The PID [1:0] bits are set to “00” (NAK)
(2) This bit is set to “1”
(3) This bit is cleared to “0”
(4) The PID [1:0] bits are set to “01” (ACK)
Rev.1.00 Nov. 30, 2004 page 69 of 131