M66591GP Datasheet, PDF (34/133 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
2.17 D0_FIFO Port Control Register 2
„ D0_FIFO Port Control Register 2 (D0_FIFOPortCtrl2)
<Address: H’34>
b15 14 13 12 11 10
BVAL BCLR FRDY
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
b
Bit name
15 BVAL
Buffer Valid Flag
14 BCLR
Buffer Clear
13
12~10
9~0
FRDY
D0_FIFO Port Ready
Reserved. Set it to “0”.
DMA_DTLN [9:0]
D0_FIFO Receive Data
9
8
7
6
5
4
3
2
1 b0
DMA_DTLN [9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
Function
<When set to OUT buffer>
• Read
0: Disables to read the data of buffer
1: Enables to read the data of buffer
• Write
Invalid (Ignored when written)
<When set to IN buffer>
• Read
0: Incomplete to write the data to buffer
1: Complete to write the data to buffer
• Write
0: Invalid (Ignored when written)
1: Enable to transmits short packet
<When set to OUT buffer>
• Write
0: Invalid (Ignored when written)
1: Buffer clear (When the BVAL bit is set to “1”)
<When set to IN buffer>
• Write
0: Invalid (Ignored when written)
1: Buffer clear (When the BVAL bit is set to “0”)
0: Disables to access the D0_FIFO Port Register 0
1: Enables to access the D0_FIFO Port Register 0
Stores the receive data length (byte count)
0
0
0
0
0
0
-
-
-
<H/W reset: H’0000>
<S/W reset: H’0000>
<USB bus reset: ->
RW
{{
“0” {
{
-
“0” “0”
{
-
(1) BVAL (Buffer Valid Flag) Bit (b15)
This bit indicates status whether or not the PIPE buffer set to the Current_PIPE [2:0] bits of the D0_FIFO Port
Control Register 0 is accessible.
When the PIPE which has been set to the Current_PIPE [2:0] bits of the D0_FIFO Port Control Register 0 is OUT,
this bit indicates whether or not data exist in the buffer.
This bit is changed from “0” to “1” in the following conditions:
(1) When the buffer has become full with a received data packet or when it has received a short packet in continuous
transfer mode.
(2) When a packet has been received up to the value preset to the TRNCNT [15:0] bits of the D0_FIFO Port Control
Register 3 with the TREnb bit of the D0_FIFO Port Control Register 0 set to “1”.
(3) When 1 packet data have been received in non-continuous transfer mode.
This bit is cleared when data are read out from the buffer, making the buffer empty. This bit may not be
automatically cleared depending on setting of the BFRE bit of the PIPE Configuration Window Register 0
corresponding to the setting PIPE having been set to the ABCR bit or the Current_PIPE [2:0] bits of the D0_FIFO
Port Control Register 0. For details, refer to the ABCR bit.
When the PIPE having been set to the Current_PIPE [2:0] bits is IN, setting “1” to this bit enables transmit of the
short packet. Further, it enables transmit of the zero-length packet by setting “1” simultaneously to this bit and to
Rev.1.00 Nov. 30, 2004 page 34 of 131