M66591GP Datasheet, PDF (23/133 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
2.10 C_FIFO Port Register 0
„ C_FIFO Port Register 0 (C_FIFOPort0)
<Address: H’14>
b15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 b0
C_FIFO_Port [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<H/W reset: H’0000>
<S/W reset: H’????>
<USB bus reset: ->
b
Bit name
Function
RW
15~0 C_FIFO_Port [15:0]
<When PIPE direction is set to OUT>
{{
C_FIFO Port
• Read
Reads receive data
<When PIPE direction is set to IN>
• Write
Writes transmit data
(1) C_FIFO_Port [15:0] (C_FIFO Port) Bits (b15-b0)
This register is a data port for FIFO buffer reading and writing by CPU access. The data written in the FIFO buffer
is sent out to USB bus in order of LSB first. The data received from the USB bus is stored in FIFO buffer in the same
order. (in the case of a 16-bit little endian)
Time
1
16
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
(The order of the data sent to USB bus)
When the PIPE direction is OUT by setting to the Current_PIPE [2:0] bits of the C_FIFO Port Control Register 0
(DIR bit of PIPE Configuration Window Register 0 is set to “0”.), it is set to receive FIFO data register.
When the PIPE direction is IN (DIR bit of PIPE Configuration Window Register 0 is set to “1”.), it is set to transmit
FIFO data register.
Further, the direction is determined by the ISEL bit of the C_FIFO Port Control Register 0 when the DCP (“000”) is
assigned to the Current_PIPE [2:0] bits. When the ISEL bit is set to “0”, it becomes the receive FIFO data register,
and when the ISEL bit is set to “1”, it becomes the transmit FIFO data register.
The corresponding bits become as follows according to the big_end bit of the Data Pin & FIFO/DMA Control Pin
Configuration Register 1:
big_end = “0” (Little endian)
When MBW bit of C_FIFO Port Control Register 0 is set to “0” (8-bit width), C_FIFO_Port [7:0] are valid.
When MBW bit of C_FIFO Port Control Register 0 is set to “1” (16-bit width), C_FIFO_Port [15:0] are valid.
C_FIFO_Port [15:8] are upper 8 bits, C_FIFO_Port [7:0] are lower 8 bits.
big_end = “1” (Big endian)
When MBW bit of C_FIFO Port Control Register 0 is set to “0”(8-bit width), C_FIFO_Port [15:8] are valid.
When MBW bit of C_FIFO Port Control Register 0 is set to “1” (16-bit width), C_FIFO_Port [15:0] are valid.
C_FIFO_Port [15:8] are lower 8 bits, C_FIFO_Port [7:0] are upper 8 bits.
Note: Only by this register can be used to access DCP FIFO buffer.
Rev.1.00 Nov. 30, 2004 page 23 of 131