M66591GP Datasheet, PDF (46/133 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
(4) CTRT (Control Transfer Stage Transition Interrupt) Bit (b11)
This bit indicates the transition of stage in control transfers.
The control transfer stage transition interrupt includes the following fifth factors:
Setup stage complete
Control write transfer status stage transition
Control read transfer status stage transition
Control transfer complete
Control transfer sequence error
These five factors can be individually enable/disable, excepting the setup stage complete.
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock (SCLK) is not supplied.
Writing “1” to this bit has no affect.
(5) BEMP (PIPE Buffer Empty/Size Error Interrupt) Bit (b10)
This bit indicates the occurrence of buffer empty or buffer size over error.
When either the PIPEB_EMP_OVR [6:1] bits or the DCP_EMP_OVR bit of the Interrupt Status Register 3 is set to
“1”, this bit is set to “1”.
This bit is cleared by clearing all the bits of the Interrupt Status Register 3.
(6) INTN (PIPE Buffer Not Ready Interrupt) Bit (b9)
This bit indicates the NAK has been responded to the host because of the buffer not ready state.
When either the PIPEB_ NRDY [6:1] bits or the DCP_ NRDY bit of the Interrupt Status Register 2 is set to “1”, this
bit is set to “1”.
This bit is cleared by clearing all the bits of the Interrupt Status Register 2.
(7) INTR (PIPE Buffer Ready Interrupt) Bit (b8)
This bit indicates the buffer ready state (that can be read/write).
When either the PIPEB_ RDY [6:1] bits or the DCP_ RDY bit of the Interrupt Status Register 1 is set to “1”, this bit
is set to “1”.
This bit is cleared by clearing all the bits of the Interrupt Status Register 1.
(8) VBUSSTS (VBUS Level Port) Bit (b7)
This bit indicates the VBUS pin state.
When this bit changes, the VBUSINT bit is set to “1”. This bit is capable of reading the correct value even if the
internal clock (SCLK) is not supplied.
As this bit directly reflects the status of the VBUS pin, the processing of reading this bit two or three times to filter
the chattering is required when executing the USB attach/detach processing by using this bit value.
(9) DVSQ [2:0] (Device State) Bits (b6-b4)
These bits indicate the present device states.
The device state conforms to description concerning the device state in chapter 9 of the Universal Serial Bus
Specification Revision 2.0.
The state after hardware resetting is the Powered state.
The state after software resetting is the Powered state.
The state after USB resetting is the Default state.
Execution of the SET_ADDRESS (Address !=“0”) brings transition into the address state, while execution of the
SET_ADDRESS (Address=“0”) brings transition into the default state.
Execution of the SET_CONFIGURATION (Configuration !=“0”) brings transition into the configured state, while
execution of the SET_CONFIGURATION (Configuration=“0”)” brings transition into the address state.
Detection of suspend brings transition into the suspend state.
(10) VALID (Setup Packet Detect) Bit (b3)
This bit indicates that the setup packet has been received.
When the setup packet is completely received, this bit is set to “1”. The interrupt does not occur with this bit.
This bit is cleared to “0” by writing “0”. This bit is not cleared when the internal clock (SCLK) is not supplied.
Writing “1” to this bit has no affect.
No writing is enabled to the PID [1:0] bits of the DCP Control Register while this bit is “1”.
Rev.1.00 Nov. 30, 2004 page 46 of 131