M66591GP Datasheet, PDF (124/133 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66591GP
4.9.13 DMA transfer read timing (when set to multiplex bus and cycle steal transfer)
DREQ
A7-1 / D15-0
ALE
CS_N
Note 4-3
RD_N
Note 4-2
DEND
17
tdis (CTRL - Dreq)
20
twh (Dreq)
32
35
tsu (A - ALE) th (A - ALE)
19 _{ten (CTRL - Dreq)}
tdis (CTRL - D) ⁶
tv (CTRL - D) 4
Address is
established
36 tw (ALE)
Data is established
ten (CTRL - D) ⁵
ta (CTRL - D) ³
Address is
established
trec (ALE) ³⁸
37
tdwr (ALE - CTRL)
42
twr (CTRL)
ta (CTRL - DendV) ¹¹
DEND is established
12
tv (CTRL - DendV)
Note 4-1: Writing through the combination of CS_N, WR0_N and WR1_N is carried out during the overlap of active (Low).
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 4-2: Reading through the combination of CS_N and RD_N is carried out during the overlap of active (Low).
The specification from the falling edge is valid from the latest active signal.
The specification from the rising edge is valid from the earliest inactive signal.
The specification of pulse width becomes valid during the overlap of active (Low).
Note 4-3: Do not change RD_N, WR0_N and WR1_N to Low concurrently with rising of CS_N.
Do not change CS_N to Low concurrently with rising of the RD_N, WR0_N or WR1_N.
In the case above, it is necessary to make an interval of 10ns or more.
Rev.1.00 Nov. 30, 2004 page 124 of 131