S124 Datasheet, PDF (59/98 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M0+ microcontroller

S124
2. Electrical Characteristics
Table 2.35 SPI timing (2/2)
Conditions: Middle drive output is selected in the Drive Strength Control bit in the PmnPFS register.
Item
Symbol
Min
Max
Unit^*1
SPI
Data output delay Master 2.7V or above t_OD
-
2.4V or above
-
14
ns
20
1.8V or above
-
25
1.6V or above
-
30
Slave 2.7V or above
-
50
2.4V or above
-
60
1.8V or above
-
85
1.6V or above
-
110
Data output hold
time
Master
Slave
t_OH
0
-
ns
0
-
Successive
transmission delay
MOSI and MISO
rise and fall time
Master
Slave
Output
t_TD
2.7V or above
2.4V or above
t_Dr, t_Df
t_SPcyc + 2 × 8 × t_SPcyc
ns
t_Pcyc
+ 2 × t_Pcyc
6 × t_Pcyc
-
-
10
ns
-
15
1.8V or above
-
20
1.6V or above
-
30
Input
-
1
µs
SSL rise and fall
time
Output 2.7V or above t_SSLr, t_SSLf
-
2.4V or above
-
10
ns
15
1.8V or above
-
20
1.6V or above
-
30
Input
-
1
µs
Slave access time
2.7V or above t_SA
-
2.4V or above
-
1.8V or above
-
1.6V or above
-
Slave output release time
2.7V or above t_REL
-
2.4V or above
-
1.8V or above
-
1.6V or above
-
Note 1. t_Pcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
2 × t_Pcyc +50 ns
2 × t_Pcyc +60
2 × t_Pcyc +85
2 × t_Pcyc +110
2 × t_Pcyc +50 ns
2 × t_Pcyc +60
2 × t_Pcyc +85
2 × t_Pcyc +110
Test conditions
Figure 2.43 to
Figure 2.48
C = 30_PF
Figure 2.47 and
Figure 2.48
C = 30_PF
R01DS0264EU0100 Rev.1.00
Feb 23, 2016
Page 59 of 95