S124 Datasheet, PDF (56/98 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M0+ microcontroller

S124
2. Electrical Characteristics
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
(n = 0, 1, 9)
Figure 2.40
t_LEAD
t_SA
t_OH
t_OD
LSB OUT
(Last data)
MSB OUT
t_SU
t_H
MSB IN
DATA
t_Dr, t_Df
DATA
SCI simple SPI mode timing (slave, CKPH = 0)
t_TD
t_LAG
t_REL
LSB OUT
LSB IN
MSB OUT
MSB IN
Table 2.34 SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Item
Symbol
Min
Simple IIC
SDA input rise time
(Standard mode) _{SDA input fall time}
t_Sr
-
t_Sf
-
SDA input spike pulse removal time
t_SP
0
Data input setup time
t_SDAS
250
Data input hold time
t_SDAH
0
SCL, SDA capacitive load
C_b*¹
-
Simple IIC
(Fast mode)
SCL, SDA input rise time
SCL, SDA input fall time
t_Sr
-
t_Sf
-
SCL, SDA input spike pulse removal time t_SP
0
Data input setup time
t_SDAS
100
Data input hold time
t_SDAH
0
SCL, SDA capacitive load
C_b*¹
-
Note: t_IICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.
Max
1000
300
4 × t_IICcyc
-
-
400
300
300
4 × t_IICcyc
-
-
400
Unit Test conditions
ns
Figure 2.41
ns
ns
ns
ns
pF
ns
Figure 2.41
ns
ns
ns
ns
pF
R01DS0264EU0100 Rev.1.00
Feb 23, 2016
Page 56 of 95