S124 Datasheet, PDF (53/98 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M0+ microcontroller

S124
2. Electrical Characteristics
Table 2.33 SCI timing (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Item
Symbol
Min
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
t_SPcyc
4
6
SCK clock high pulse width
t_SPCKWH
0.4
SCK clock low pulse width
t_SPCKWL
0.4
SCK clock rise and fall time
1.8V or above ^tSPCKr,
-
1.6V or above ^tSPCKf
-
Data input setup
Master 2.7V or above t_SU
45
time
2.4V or above
55
1.8V or above
80
1.6V or above
110
Slave 2.7V or above
40
1.6V or above
45
Data input hold time Master
Slave
t_H
33.3
40
SS input setup time
t_LEAD
1
SS input hold time
t_LAG
1
Data output delay Master 1.8V or above t_OD
-
1.6V or above
-
Slave 2.4V or above
-
1.8V or above
-
1.6V or above
-
Data output hold
Master 2.7V or above t_OH
–10
time
2.4V or above
–20
1.8V or above
–30
1.6V or above
–40
Slave
–10
Data rise and fall Master
t_Dr, t_Df
-
time
Slave 1.8V or above
-
1.6V or above
-
Simple Slave access time
SPI
Slave output release time
t_SA
-
t_REL
-
Note 1. t_Pcyc: PCLKB cycle
Max
65536
65536
0.6
0.6
20
30
-
-
-
-
-
-
-
-
-
-
40
50
65
100
125
-
-
-
-
-
20
20
30
6
6
Unit*¹
t_Pcyc
Test conditions
Figure 2.36
t_SPcyc
t_SPcyc
ns
ns
Figure 2.37 to
Figure 2.40
ns
t_SPcyc
t_SPcyc
ns
ns
ns
t_Pcyc
t_Pcyc
Figure 2.40
R01DS0264EU0100 Rev.1.00
Feb 23, 2016
Page 53 of 95