S124 Datasheet, PDF (40/98 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M0+ microcontroller

S124
2. Electrical Characteristics
Table 2.18 Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Item
Operation
frequency
Symbol Min
Typ
Max
System clock (ICLK)*^1, *^2, *⁴
1.8 to 5.5 V
f
0.032768
-
1
Peripheral module clock (PCLKB)*⁴
1.8 to 5.5 V
-
-
1
Peripheral module clock (PCLKD)*^3, *⁴ 1.8 to 5.5 V
-
-
1
Unit
MHz
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Table 2.19 Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Item
Operation
frequency
Symbol Min
Typ
Max
System clock (ICLK)*^1, *^2, *⁴
1.6 to 5.5 V
f
0.032768
-
4
Peripheral module clock (PCLKB)*⁴
1.6 to 5.5 V
-
-
4
Peripheral module clock (PCLKD)*^3, *⁴ 1.6 to 5.5 V
-
-
4
Unit
MHz
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Table 2.20 Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Item
Operation
frequency
Symbol Min
Typ
Max
Unit
System clock (ICLK)*^1, *³
1.8 to 5.5 V
f
27.8528 32.768 37.6832
kHz
Peripheral module clock (PCLKB)*³
1.8 to 5.5 V
-
-
37.6832
Peripheral module clock (PCLKD)*^2, *³ 1.8 to 5.5 V
-
-
37.6832
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
R01DS0264EU0100 Rev.1.00
Feb 23, 2016
Page 40 of 95