PD44165084B_15 Datasheet, PDF (34/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
TAP Controller State Diagram
1
Test-Logic-Reset
0
1
0
Run-Test / Idle
1
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR
1
Exit1-DR
0
0
1
Pause-DR
0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
1
Exit1-IR
0
0
1
Pause-IR
0
1
0
Exit2-IR
1
Update-IR
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to V_SS to preclude mid level inputs. TDI and TMS may be left open
but fix them to V_DD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 34 of 39