PD44165084B_15 Datasheet, PDF (16/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
Bus Cycle State Diagram
LOAD NEW
WRITE ADDRESS;
W_Count = 0
Always W# = LOW & W_Count = 4
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
R# = LOW & R_Count = 4 Always
W# = LOW
R_Init = 0
WRITE DOUBLE;
W_Count = W_Count+2
W_Count = 2 Always
INCREMENT WRITE
ADDRESS BY TWO
R# = HIGH
& R_Count = 4
W# = HIGH
& W_Count = 4
READ DOUBLE;
R_Count = R_Count+2
R_Count = 2 Always
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
R# = LOW
W# = HIGH
R# = HIGH
WRITE PORT NOP
Power UP
Supply voltage
Supply voltage
provided
provided
READ PORT NOP
R_Init = 0
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
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