PD44165084B_15 Datasheet, PDF (33/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
EXTEST
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
SRAM Status
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Boundary Scan Register Status
CQ,CQ#
Q
Pad
Pad
Pad
Pad
−
−
−
−
Pad
Pad
Pad
Pad
Internal
Internal
Internal
Pad
−
−
−
−
Note
No definition
No definition
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
There are two statuses:
Boundary Scan
Register
CAPTURE
Register
Pad : Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
Update
Pad
Register
QDR
Pad
SRAM
Output
Driver
Internal
SRAM
Output
High-Z
JTAG ctrl
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 33 of 39