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PD44165084B_15 Datasheet, PDF (18/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Note
Input leakage current
ILI
I/O leakage current
ILO
X8 X9 x18 x36
−2
+2
μA
−2
+2
μA
Operating supply current IDD VIN ≤ VIL or VIN ≥ VIH, -E33
520 520 580 740 mA
(Read cycle / Write cycle)
II/O = 0 mA,
-E35
500 500 560 710
Cycle = MAX.
-E40
460 460 520 650
-E50
410 410 460 570
Standby supply current
ISB1 VIN ≤ VIL or VIN ≥ VIH, -E33
390 390 400 430 mA
(NOP)
II/O = 0 mA,
-E35
390 390 390 420
Cycle = MAX.
-E40
370 370 380 400
Inputs static
-E50
350 350 350 370
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ−0.2
VDDQ/2−0.12
VSS
VDDQ/2−0.12
VDDQ
VDDQ/2+0.12
0.2
VDDQ/2+0.12
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 18 of 39