PD44165084B_15 Datasheet, PDF (14/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
Byte Write Operation
[μPD44165084B]
Operation
Write D0 to D7
Write D0 to D3
Write D4 to D7
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
NW0#
0
0
0
0
1
1
1
1
NW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44165094B]
Operation
Write D0 to D8
Write nothing
K
L→H
−
L→H
−
K#
−
L→H
−
L→H
BW0#
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44165184B]
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 14 of 39