PD44165084B_15 Datasheet, PDF (29/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register
Boundary register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
107
bit
ID Register Definition
Part number
Organization
μPD44165084B
μPD44165094B
μPD44165184B
μPD44165364B
2M x 8
2M x 9
1M x 18
512K x 36
ID [31:28] vendor
revision no.
XXXX
XXXX
XXXX
XXXX
ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit
0000 0000 0000 1111 00000010000
1
0000 0000 0101 0010 00000010000
1
0000 0000 0001 0000 00000010000
1
0000 0000 0001 0001 00000010000
1
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 29 of 39