PD44165084B_15 Datasheet, PDF (23/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. V_DD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once V_DD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. V_DDQ is 1.5 V DC.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
Page 23 of 39