PD44165084B_15 Datasheet, PDF (19/40 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD44165084B, μPD44165094B , μPD44165184B, μPD44165364B
DC Characteristics 2 (TA = −40 to 85°C, V_DD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Note
Input leakage current
I_LI
I/O leakage current
I_LO
X8 X9 x18 x36
−2
+2
μA
−2
+2
μA
Operating supply current I_DD V_IN ≤ V_IL or V_IN ≥ V_IH, -E33Y
640 640 710 870 mA
(Read cycle / Write cycle)
I_I/O = 0 mA,
-E35Y
620 620 690 840
Cycle = MAX.
-E40Y
580 580 650 780
-E50Y
530 530 590 700
Standby supply current
I_SB1 V_IN ≤ V_IL or V_IN ≥ V_IH, -E33Y
510 510 520 550 mA
(NOP)
I_I/O = 0 mA,
-E35Y
510 510 510 540
Cycle = MAX.
-E40Y
490 490 500 520
Inputs static
-E50Y
470 470 470 490
Output HIGH voltage
Output LOW voltage
V_OH(Low) |I_OH| ≤ 0.1 mA
V_OH Note1
V_OL(Low) I_OL ≤ 0.1 mA
V_OL Note2
V_DDQ−0.2
V_DDQ/2−0.12
V_SS
V_DDQ/2−0.12
V_DDQ
V_DDQ/2+0.12
0.2
V_DDQ/2+0.12
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | I_OH | = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. I_OL = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0018EJ0200 Rev.2.00
October 6, 2011
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