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HD6413258F10V Datasheet, PDF (27/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. | |||
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External memory is accessed a byte at a time in three or more states. The basic bus cycle is three
states, but additional wait states can be inserted on request.
2.3.2 IOS
There are two gaps in the on-chip address space above the on-chip RAM. Addresses HâFF80 to
HâFF8F, situated between the on-chip RAM and register field, are off-chip. Addresses HâFFA0 to
HâFFAF are also off-chip. These 32 addresses can be conveniently assigned to external I/O devices.
To simplify the addressing of devices at these addresses, an IOS signal is provided that goes low
when the CPU accesses addresses HâFF00 to HâFFFF. The IOS signal can be used in place of the
upper 8 bits of the address bus.
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