HD6413258F10V Datasheet, PDF (151/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

Sampling signal
FTI
input
DCQ
Latch
DCQ
Latch
DCQ
Latch
DCQ
Latch
Agreement
detector
Noise
canceler
output
Sampling signal
∆ tt
∆tt:: sseelelecctteeddbbyyNNCCSS11aannddNNCCSS00
Figure 7-14. Noise Canceler Block Diagram
Table 7-4. Sampling Clock Cycle for Various System Clock Frequencies
NCS1
0
0
1
1
NCS0
0
1
0
1
Sampling
clock 10
—
—
Ø/32
3.2
Ø/64
6.4
Ø/128 12.8
System clock (Ø) frequency (MHz)
8
6
4
2
1
0.5
—
——
—
—
—
4.0 5.3 8.0 16.0 32.0 64.0
8.0 10.7 16.0 32.0 64.0 128.0
16.0 21.3 32.0 64.0 128.0 2Fi5g67.-014
(Unit: µs)
Figure 7-15 shows an example of noise cancellation. In this example, an input capture pulse
narrower than four sampling clock cycles is rejected as noise.
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