HD6413258F10V Datasheet, PDF (162/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

Bit 7
CMIEB
0
1
Description
Compare-match interrupt request B (CMIB) is disabled.
Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
Bit 6 – Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to 1.
Bit 6
CMIEA
0
1
Description
Compare-match interrupt request A (CMIA) is disabled.
Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
Bit 5 – Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR)
is set to 1.
Bit 5
OVIE
0
1
Description
The timer overflow interrupt request (OVI) is disabled.
The timer overflow interrupt request (OVI) is enabled.
(Initial value)
Bits 4 and 3 – Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 4
CCLR1
0
0
1
1
Bit 3
CCLR0
0
1
0
1
Description
Not cleared.
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
(Initial value)
Bits 2, 1, and 0 – Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or
external clock source for the timer counter. For the external clock source they select whether to
increment the count on the rising or falling edge of the clock input, or on both edges. For the
internal clock sources the count is incremented on the falling edge of the clock input.
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