HD6413258F10V Datasheet, PDF (245/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

15.2.2 AC Characteristics
The AC characteristics of the H8/325 series are listed in three tables. Bus timing parameters are
given in table 15-6, control signal timing parameters in table 15-7, and timing parameters of the on-
chip supporting modules in table 15-8.
Table 15-6. Bus Timing
Condition A: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 2.7 to 3.6V, VSS = 0V, Ta = –20 to 75˚C, for only H8/3257 and H8/3256
Condition B
Condition A
5MHz
6MHz
8MHz
10MHz
Measurement
Item
Symbol min max min max min max min max Unit conditions
Clock cycle time
tcyc
200 2000 166.7 2000 125 2000 100 2000 ns Fig. 15-4
Clock pulse width Low tCL
65 – 65 – 45 – 35 – ns Fig. 15-4
Clock pulse width High tCH
65 – 65 – 45 – 35 – 1ns Fig. 15-4
Clock rise time
tCr
– 25 – 15 – 15 – 15 ns Fig. 15-4
Clock fall time
tCf
– 25 – 15 – 15 – 15 ns Fig. 15-4
Address delay time
tAD
–
90 – 70 –
60 – 55 ns Fig. 15-4
Address hold time
tAH
30 –
30 – 25 – 20 –
ns Fig. 15-4
Address strobe delay time tASD – 80 – 70 – 60 – 40 ns Fig. 15-4
Write strobe delay time tWSD – 80 – 70 – 60 – 50 ns Fig. 15-4
Strobe delay time
tSD
– 90 – 70 – 60 – 50 ns Fig. 15-4
Write strobe pulse width tWSW 200 – 200 – 150 – 120 – ns Fig. 15-4
Address setup time 1
tAS1
25 –
25 –
20 –
15 –
ns Fig. 15-4
Address setup time 2
tAS2
105 –
105 –
80 –
65 –
ns Fig. 15-4
Read data setup time
tRDS
90 –
60 –
50 –
35 –
ns Fig. 15-4
Read data hold time
tRDH
0
–
0
–
0
–
0
–
ns Fig. 15-4
Write data delay time tWDD – 125 – 85 – 75 – 75 ns Fig. 15-4
Read data access time tACC – 300 – 280 – 210 – 170 ns Fig. 15-4
Write data setup time tWDS 10 – 30 – 15 – 10 – ns Fig. 15-4
Write data hold time
tWDH 30 –
30 –
25 –
20 –
ns Fig. 15-4
Wait setup time
tWTS
60 –
45 –
45 –
45 –
ns Fig. 15-5
Wait hold time
tWTH 20 –
10 –
10 –
10 –
ns Fig. 15-5
E clock delay time
tED
– 30 – 25 – 25 – 25 ns Fig. 15-6
E clock rise time
tEr
– 25 – 15 – 15 – 15 ns Fig. 15-6
E clock fall time
tEf
– 25 – 15 – 15 – 15 ns Fig. 15-6
Read data hold time
tRDHE 0
–
0
–
0
–
0
–
ns Fig. 15-6
(for E clock)
Write data hold time
tWDHE 60 –
50 –
40 –
30 –
ns Fig. 15-6
(for E clock)
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