HD6413258F10V Datasheet, PDF (128/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

Ø
Port 3
Port 3 write
Port 3 write
OS
Not output
Figure 6-3. Output Strobe Output Timing
(Consecutive Writing of Port 3 When OSS = 1)
6.3.2 Busy Signal Output Timing
The busy signal remains low from the fall of the input strobe signal until the data latched in port 3
have been read, unlocking the latch. Figure 6-4 shows an example.
While the busy signal is low, data input to port 3 are not latched, even if the input strobe signal goes
low again.
Ø
IS
BUSY
Port 3 read
Fig 6-3
Figure 6-4. Busy Signal Output Timing
6.3.3 Operation in Software Standby Mode
In software standby mode, the OS and BUSY output pins retain their previous states.
For timing of the output strobe signal, the entire time during when the chip is in software standby
mode is counted as zero system clock cycles. Figure 6-5 shows an example.
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