HD6413258F10V Datasheet, PDF (227/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

12.4.1 Transition to Software Standby Mode
To enter the software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to 1, then execute the SLEEP instruction.
12.4.2 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of seven pins: NMI,
IRQ0, IRQ1, IRQ2, IS, RES, or STBY.
(1) Recovery by External Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, or input strobe (ISI)
interrupt request signal is received, the clock oscillator begins operating. After the waiting time set
in the system control register (bits STS2 to STS0), clock pulses are supplied to the CPU and on-
chip supporting modules. The CPU executes the interrupt-handling sequence for the requested
interrupt, then returns to the instruction after the SLEEP instruction. The SSBY bit is not cleared.
See Section 12.2, System Control Register: Power-Down Control Bits for information about the
STS bits.
(2) Recovery by RES Pin: When the RES pin goes low, the clock oscillator starts. Next, when
the RES pin goes high, the CPU begins executing the reset sequence. The SSBY bit is cleared to 0.
The RES pin must be held low long enough for the clock to stabilize.
(3) Recovery by STBY Pin: When the STBY pin goes low, the chip exits from the software
standby mode to the hardware standby mode.
12.4.3 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when NMI goes low and exits when
NMI goes high, as shown in figure 12-1.
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