HD6413258F10V Datasheet, PDF (127/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

Bit 2—Busy Enable (BSE): This bit enables or disables output of the busy signal. Do not set BSE
to 1 in the expanded modes (modes 1 and 2).
Bit 2
ISIE
0
1
Description
Busy signal output is disabled.
Busy signal output is enabled.
(Initial value)
Bits 1 and 0—Reserved: These bits cannot be modified and are always read as 1.
6.3 Operation
6.3.1 Output Timing of Output Strobe Signal
The output strobe signal is output when the port 3 data register (P3DR) is written or read. The
output strobe signal goes low at the seventh system clock cycle after P3DR is written or read,
remains low for eight system clock cycles, then goes high. Figure 6-2 shows how the output strobe
signal is output after P3DR is written (when OSS = 1).
Note the following point when reading or writing P3DR twice consecutively.
If P3DR is written or read once, then written or read again within 15 states, the output strobe signal
is not output for the second write or read. Figure 6-3 shows an example of this when OSS = 1.
Ø
Port 3
Port 3 write
OS
7 system clocks 8 system clocks
Figure 6-2. Output Strobe Output Timing (When OSS = 1)
118