M37221M6_03 Datasheet, PDF (25/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
(8) START/STOP Condition Detecting Condi-
tions
The START/STOP condition detecting conditions are shown in Fig-
ure 21 and Table 5. Only when the 3 conditions of Table 5 are satis-
fied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” occurs to the
CPU.
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Setup
time
Hold time
Setup
time
Hold time
Fig. 21. START condition/STOP condition detecting timing diagram
Table 5. START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
6.5 µs (26 cycles) < SCL release 1.0 µs (4 cycles) < SCL release
time
time
3.25 µs (13 cycles) < Setup time 0.5 µs (2 cycles) < Setup time
3.25 µs (13 cycles) < Hold time 0.5 µs (2 cycles) < Hold time
Note: Absolute time at φ = 4 MHz. The value in parentheses de-
notes the number of φ cycles.
(9) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
Œ7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I²C control register (address 00DA16) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I²C address register (address
00D816). At the time of this comparison, address comparison of
the RBW bit of the I²C address register (address 00D816) is not
made. For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 22, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I²C control register (address 00DA16) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I²C address
register (address 00D816). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I²C address regis-
ter (address 00D816) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A
Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Sr
Slave address
1st 7 bits
R/W
Data
A
Data
A
P
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 22. Address data communication format
From master to slave
From slave to master
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