M37221M6_03 Datasheet, PDF (19/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I²C-BUS INTERFACE
The multi-master I²C-BUS interface is a circuit for serial communica-
tions conformed with the Philips I²C-BUS data transfer format. This
interface, having an arbitration lost detection function and a synchro-
nous function, is useful for serial communications of the multi-mas-
ter.
Figure 12 shows a block diagram of the multi-master I²C-BUS inter-
face and Table 2 shows multi-master I²C-BUS interface functions.
This multi-master I²C-BUS interface consists of the I²C address reg-
ister, the I²C data shift register, the I²C clock control register, the I²C
control register, the I²C status register and other control circuits.
Table 2. Multi-master I²C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
Function
In conformity with Philips I²C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
trol function (bits 6 and 7 of the I²C control register at address
00DA16) for connections between the I²C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
Serial
data
(SDA)
Noise
elimination
circuit
b7
I²C address register
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
S0D
Address comparator
Data
control ^b7
b0
circuit
I²C data shift register
S0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
b0
AL AAS AD0 LRB
MST TRX BB PIN
AL
circuit
BB
circuit
S1
Internal data bus
I²C status
register
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
b0
b7
b0
ACK
ACK
BIT
FAST
MODE
CCR4
CCR3
CCR2
CCR1
CCR0
S2
I²C clock control register
BSEL1
BSEL0
10BIT
SAD
ALS
ESO BC2
BC1
BC0
S1D _I2_{C control register}
Clock division
System clock (φ)
Bit counter
Fig. 12. Block diagram of multimaster I²C-BUS interface
18