M37221M6_03 Datasheet, PDF (17/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Internal clock—the serial I/O counter is set to “7” during write cycle
into the serial I/O register (address 00DD16), and transfer clock goes
“H” forcibly. At each falling edge of the transfer clock after the write
cycle, serial data is output from the SOUT pin. Transfer direction can
be selected by bit 5 of the serial I/O mode register. At each rising
edge of the transfer clock, data is input from the SIN pin and data in
the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at “H.” At this time the inter-
rupt request bit is set to “1.”
External clock—when an external clock is selected as the clock
source, the interrupt request is set to “1” after the transfer clock has
counted 8 times. However, transfer operation does not stop, so con-
trol the clock externally. Use the external clock of 1MHz or less with
a duty cycle of 50%.
The serial I/O timing is shown in Figure 10. When using an external
clock for transfer, the external clock must be held at “H” for initializing
the serial I/O counter. When switching between an internal clock and
an external clock, do not switch during transfer. Also, be sure to ini-
tialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in-
structions as SEB and CLB instructions.
2: When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the
transfer clock input level.
7
0
0
Serial I/O mode register
(SM : address 00DC16)
Internal synchronizing clock
selection bits
b1 b0
0 0 : f(XIN)/4
0 1 : f(XIN)/16
1 0 : f(XIN)/32
1 1 : f(XIN)/64
Synchronizing clock selection bit
0 : External clock
1 : Internal clock
Serial I/O port selection bit
0 : P20, P21 functions as port
1 : SCLK, SOUT
Fix this bit to “0.”
Transfer direction selection bit
0 : LSB first
1 : MSB first
Serial input pin selection bit
0 : Input signal from SIN pin
1 : Input signal from SOUT pin
Fig. 9. Structure of serial I/O mode register
Synchroninzing clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
Serial I/O input
SIN
D0
D1
D2
D3
D4
D5
D6
(Note)
D7
Interrupt request bit is set to “1”
Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 10. Serial I/O timing (for LSB first)
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