M37221M6_03 Datasheet, PDF (21/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
7
0
ACK ^{ACK FAST} CCR4 CCR3 CCR2 CCR1 CCR0 ^{I2C clock control register}
BIT MODE
(S2 : address 00DB16)
SCL frequency
control bits
Refer to Table 3.
SCL mode
specification bit
0 : Standard clock
mode
1 : High-speed clock
mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Fig. 14. Structure of I²C clock control register
Table 3. Set values of I²C clock control register and SCL frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
SCL frequency
(at φ = 4MHz, unit : kHz)
Standard clock High-speed clock
mode
mode
0 0 0 0 0 Setting disabled Setting disabled
0 0 0 0 1 Setting disabled Setting disabled
0 0 0 1 0 Setting disabled Setting disabled
0 0 0 1 1 Setting disabled
333
0 0 1 0 0 Setting disabled
250
00101
100
400(Note)
00110
83.3
166
500/CCR value 1000/CCR value
11101
17.2
34.5
11110
16.6
33.3
11111
16.1
32.3
Note: At 400 kHz in the high-speed clock mode, the duty is 40%.
In the other cases, the duty is 50%.
(4) I²C Control Register
The I²C control register (address 00DA16) controls data communica-
tion format.
s Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
s Bit 3: I²C interface use enable bit (ES0)
This bit enables to use the multimaster I²C BUS interface. When this
bit is set to “0,” the use disable status is provided, so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
When ES0 = “0,” the following is performed.
• ^{PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C}
status register at address 00D916 ).
• ^{Writing data to the I2C data shift register (address 00D716) is dis-}
abled.
s Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “(5) I²C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
s Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I²C address register (ad-
dress 00D816) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I²C
address register are compared with address data.
s Bits 6 and 7: Connection control bits between I²C-BUS interface
and ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 15).
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