M37221M6_03 Datasheet, PDF (13/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37221M6-XXXSP has 4 timers: timer 1, timer 2, timer 3, and
timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer
block diagram is shown in Figure 7.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. The value is set to a timer at the same time
by writing a count value to the corresponding timer latch (addresses
00F016 to 00F316).
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse after the count
value reaches “0016”.
(1) Timer 1
Timer 1 can select one of the following count sources:
• ^f(XIN)/16
• ^f(XIN)/4096
The count source of timer 1 is selected by setting bit 0 of the timer 12
mode register (address 00F416).
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
• ^f(XIN)/16
• ^{Timer 1 overflow signal}
• ^{External clock from the P24/TIM2 pin}
The count source of timer 2 is selected by setting bits 4 and 1 of the
timer 12 mode register (address 00F416). When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
(3) Timer 3
Timer 3 can select one of the following count sources:
• ^f(XIN)/16
• ^{External clock from the HSYNC pin}
• ^{External clock from the P23/TIM3 pin}
The count source of timer 3 is selected by setting bits 5 and 0 of the
timer 34 mode register (address 00F516)
Timer 3 interrupt request occurs at timer 3 overflow.
(4) Timer 4
Timer 4 can select one of the following count sources:
• ^f(XIN)/16
• ^f(XIN)/2
• ^{Timer 3 overflow signal}
The count source of timer 3 is selected by setting bits 4 and 1 of the
timer 34 mode register (address 00F516). When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se-
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow at these state, the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN)/16 is not selected as the timer 3 count source.
So set bit 0 of the timer 34 mode register (address 00F516) to “0”
before the execution of the STP instruction (f(XIN)/16 is selected as
the timer 3 count source). The internal STP state is released by timer
4 overflow at these state, the internal clock is connected.
Because of this, the program starts with the stable clock.
The structure of timer-related registers is shown in Figure 6.
12