M37221M6_03 Datasheet, PDF (22/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
SCL
Multi-master
I²C-BUS
interface
SDA
“0”
“1” BSEL0
SCL1/P11
“0”
“1” BSEL1
SCL2/P12
“0”
“1” BSEL0
SDA1/P13
“0”
“1” BSEL1
SDA2/P14
Fig. 15. Connection port control by BSEL0 and BSEL1
(5) I²C Status Register
The I²C status register (address 00D916) controls the I²C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
s Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by execut-
ing a write instruction to the I²C data shift register (address 00D716).
s Bit 1: General call detecting flag (AD0)
This bit is set to “1” when a general call^V whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START con-
dition.
VGeneral call: The master transmits the general call address “0016”
to all slaves.
s Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
ŒIn the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
•^{The address data immediately after occurrence of a START}
condition agrees with the slave address stored in the high-order
7 bits of the I²C address register (address 00D816).
•^{A general call is received.}
In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
•^{When the address data is compared with the I2C address}
register (8 bits consisted of slave address and RBW), the first
bytes agree.
Ž The state of this bit is changed from “1” to “0” by executing a write
instruction to the I²C data shift register (address 00D716).
7
0
BSEL1 BSEL0 ^{10 BIT} ALS
SAD
ES0
BC2
BC1
BC0
I²C control register
(S1D : address 00DA16)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 :8
0 0 1 :7
0 1 0 :6
0 1 1 :5
1 0 0 :4
1 0 1 :3
1 1 0 :2
1 1 1 :1
I²C-BUS interface use
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
Connection control bits
between I²C-BUS
interface and ports
b7 b6 Connection port
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1,
SCL2, SDA2
Fig. 16. Structure of I²C control register
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