CSR1001A04-IQQA-R Datasheet, PDF (27/45 Pages) –

5.4 Programming and Debug Interface
Important Note:
The CSR1001 QFN debug SPI interface is available in SPI slave mode to enable an external MCU to program
and control the CSR1001 QFN, generally via libraries or tools supplied by CSR. The protocol of this interface
is proprietary. The 4 SPI debug lines directly support this function.
The SPI programs, configures and debugs the CSR1001 QFN. It is required in production. Ensure the 4 SPI
signals are brought out to either test points or a header.
Take SPI_PIO#_SEL high to enable the SPI debug feature on PIO[8:5].
CSR1001 QFN uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when
the internal processor is running or is stopped.
Data is written or read one word at a time, or the auto-increment feature is available for block access.
5.4.1 Instruction Cycle
The CSR1001 QFN is the slave and receives commands on DEBUG_MOSI and outputs data on DEBUG_MISO.
Table 5.3 shows the instruction cycle for a SPI transaction.
1 Reset the SPI interface
2 Write the command word
3 Write the address
4 Write or read data words
5 Termination
Hold DEBUG_CS# high for 2 DEBUG_CLK cycles
Take DEBUG_CS# low and clock in the 8-bit command
Clock in the 16-bit address word
Clock in or out 16-bit data word(s)
Take DEBUG_CS# high
Table 5.3: Instruction Cycle for a SPI Transaction
With the exception of reset, DEBUG_CS# must be held low during the transaction. Data on DEBUG_MOSI is clocked
into the CSR1001 QFN on the rising edge of the clock line DEBUG_CLK. When reading, CSR1001 QFN replies to
the master on DEBUG_MISO with the data changing on the falling edge of the DEBUG_CLK. The master provides
the clock on DEBUG_CLK. The transaction is terminated by taking DEBUG_CS# high.
The auto increment operation on the CSR1001 QFN cuts down on the overhead of sending a command word and
the address of a register for each read or write, especially when large amounts of data are to be transferred. The
auto increment offers increased data transfer efficiency on the CSR1001 QFN. To invoke auto increment,
DEBUG_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra
word written or read.
5.4.2 Multi-slave Operation
Do not connect the CSR1001 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines.
When CSR1001 QFN is deselected (DEBUG_CS# = 1), the DEBUG_MISO line does not float. Instead,
CSR1001 QFN outputs 0 if the processor is running or 1 if it is stopped.
Production Information
© Cambridge Silicon Radio Limited 2011-2013
Page 26 of 44
CS-216358-DSP5
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