CSR1001A04-IQQA-R Datasheet, PDF (14/45 Pages) –

PIO Port
PIO[7] /
DEBUG_MOSI
PIO[6] /
DEBUG_CS#
PIO[5] /
DEBUG_CLK
PIO[4] /
SF_CS#
Lead Pad Type
Supply Domain
Bidirectional with
34 programmable strength VDD_PADS
internal pull-up/down
Bidirectional with
31 programmable strength VDD_PADS
internal pull-up/down
Bidirectional with
28 programmable strength VDD_PADS
internal pull-up/down
Bidirectional with
25 programmable strength VDD_PADS
internal pull-up/down
PIO[3] /
SF_DIN
Bidirectional with
24 programmable strength VDD_PADS
internal pull-up/down
PIO[2]
PIO[1] /
UART_RX
PIO[0] /
UART_TX
AIO[2]
AIO[1]
AIO[0]
Bidirectional with
52 programmable strength VDD_PADS
internal pull-up/down
Bidirectional with
21 programmable strength VDD_PADS
internal pull-up/down
Bidirectional with
19 programmable strength VDD_PADS
internal pull-up/down
16
17 Bidirectional analogue VDD_AUX^(c)
18
(c) _{The VDD_AUX domain is generated from VDD_REG_IN, see Figure 6.1.}
Test and Debug
SPI_PIO#
Lead Pad Type
50
Input with strong
internal pull-down
Supply Domain
VDD_PADS
Wake-up
WAKE
Lead Pad Type
Supply Domain
Input has no internal
6 pull-up or pull-down, VDD_BAT
use external pull-down.
Description
Programmable I/O line or debug SPI
MOSI selected by SPI_PIO#
Programmable I/O line or debug SPI chip
select (CS#) selected by SPI_PIO#.
Programmable I/O line or debug SPI
CLK selected by SPI_PIO#.
Programmable I/O line or SPI serial flash
chip select (SF_CS#), see Section 5.3.
Programmable I/O line or SPI serial flash
data (SF_DIN) input. If connecting to SPI
serial flash, this pin connects to SI on the
serial flash. See Section 5.3.
Programmable I/O line or I²C power.
Programmable I/O line or UART RX.
Programmable I/O line or UART TX.
Analogue programmable I/O line.
Description
Selects SPI debug on PIO[8:5].
Description
Input to wake CSR1001 QFN from
hibernate or dormant.
Production Information
© Cambridge Silicon Radio Limited 2011-2013
Page 13 of 44
CS-216358-DSP5
www.csr.com