CSR1001A04-IQQA-R Datasheet, PDF (19/45 Pages) –

3 Clock Generation
The Bluetooth reference clock for the system is generated from an external 16MHz clock source, see Figure 3.1. All
the CSR1001 QFN internal digital clocks are generated using a phase locked loop, which is locked to the frequency
of either the external reference clock source or a sleep clock frequency of 32.768kHz, see Figure 3.1.
3.1 Clock Architecture
Bluetooth PLL
Bluetooth LO
(~4.8GHz)
Fast XTAL Clock
for System
16MHz
Core Digits
(16MHz)
Slow XTAL Clock
for Sleep
32kHz
Embedded Digits
(32kHz)
Figure 3.1: Clock Architecture
3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT
CSR1001 QFN contains crystal driver circuits. This operates with an external crystal and capacitors to form a Pierce
oscillator. Figure 3.2 shows the external crystal is connected to pins XTAL_16M_IN and XTAL_16M_OUT.
-
C_TRIM
C
LOAD1
C_LOAD2
Figure 3.2: Crystal Driver Circuit
Production Information
© Cambridge Silicon Radio Limited 2011-2013
Page 18 of 44
CS-216358-DSP5
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