CSR1001A04-IQQA-R Datasheet, PDF (21/45 Pages) –

3.3 Sleep Clock
The sleep clock is an externally provided 32.768kHz clock that is used during deep sleep and in other low-power
modes. Figure 3.3 shows the sleep clock crystal driver circuit.
-
C_LOAD1
C_LOAD2
Figure 3.3: Sleep Clock Crystal Driver Circuit
Note:
C_LOAD1 and C_LOAD2 in combination with any parasitic capacitance provide the load capacitance required by the
crystal.
3.3.1 Crystal Specification
Table 3.2 shows the requirements for the sleep clock.
Sleep Clock
Frequency
Frequency tolerance^{(a) (b)}
Frequency trim range
Drive level
Load capacitance
Equivalent series resistance
Duty cycle
Min
30
-
-
-
-
40
30:70
Typ
32.768
-
50
0.4
-
-
50:50
Max
35
250
-
-
1
65
70:30
Units
kHz
±ppm
±ppm
V
pF
kΩ
%
Table 3.2: Sleep Clock Specification
(a) _{The frequency of the slow clock is periodically calibrated against the system clock. As a result the rate of change of the frequency is more}
important than the maximum deviation. To meet the accuracy requirements the frequency should not drift due to temperature or other effects
by more than 80ppm in any 5 minute period.
(b) _{CSR1001 QFN can correct for ±1% by using the fast clock to calibrate the slow clock.}
Production Information
© Cambridge Silicon Radio Limited 2011-2013
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