CSR1001A04-IQQA-R Datasheet, PDF (26/45 Pages) –

Figure 5.2 shows simple SPI timing diagram.
SF_CS#
SF_CLK
SF_DOUT
MSB
LSB
SF_DIN
MSB
LSB
Figure 5.2: SPI Timing Diagram
The boot-up sequence for CSR1001 QFN is controlled by hardware and firmware. Figure 5.3 shows the sequence
of loading RAM with content from RAM, EEPROM and SPI serial flash.
Device Starts
Hardware Copies
Content of ROM to RAM
Hardware Checks I ²C
Interface (Default Pins )
Hardware Checks SPI
Interface (Default Pins )
No
Presence of
EEPROM Device
Yes
Copy Content of
EEPROM to RAM
Presence of SPI
Serial Flash Device
Yes
Copy Content of SPI
Serial Flash to RAM
No
Start MCU Executing
from RAM
Figure 5.3: Memory Boot-up Sequence
Production Information
© Cambridge Silicon Radio Limited 2011-2013
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CS-216358-DSP5
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