CSR1001A04-IQQA-R Datasheet, PDF (25/45 Pages) –

Figure 5.1 shows an example of an EEPROM connected to the I²C interface where I2C_SCL, I2C_SDA and PIO[2]
are connected to the external EEPROM. The PIO[2] pin supplies the power to the EEPROM supply pin, e.g. VDD.
At boot-up, if there is no valid ROM image in the CSR1001 QFN ROM area the CSR1001 QFN tries to boot from
the I²C interface, see Figure 5.3. This involves reading the code from the external EEPROM and loading it into the
internal CSR1001 QFN RAM.
PIO[2]
I2C_SCL
I2C_SDA
24AA512
8
VDD
7
WP
6
SCL
5
SDA
1
A0
2
A1
3
A2
4
VSS
Figure 5.1: Example of an I²C Interface EEPROM Connection
5.3 SPI Master Interface
The SPI master memory interface in the CSR1001 QFN is overlaid on the I²C interface and uses a further 3 PIOs
for the extra pins, see Table 5.2.
SPI Flash Interface
Flash_VDD
SF_DIN
SF_CS#
SF_CLK
SF_DOUT
Pin
PIO[2]
PIO[3]
PIO[4]
I2C_SCL
I2C_SDA
Table 5.2: SPI Master Serial Flash Memory Interface
Note:
If an application using CSR1001 QFN is designed to boot from SPI serial flash, it is possible for the firmware to
map the I²C interface to alternative PIOs.
Production Information
© Cambridge Silicon Radio Limited 2011-2013
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CS-216358-DSP5
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