HYB25DC512800B Datasheet, PDF (9/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
2.2
Configuration of PG-TFBGA-60
The ball configuration of a DDR SDRAM is listed by function in Table 6. The abbreviations used in the Pin#/Buffer# column are
explained in Table 7 and Table 8 respectively.
Ball#/Pin#
Name
Clock Signals
G2
CK1
G3
CK1
H3
CKE
Control Signals
H7
RAS
G8
CAS
G7
WE
H8
CS
Address Signals
J8
BA0
J7
BA1
K7
A0
L8
A1
L7
A2
M8
A3
M2
A4
L3
A5
L2
A6
K3
A7
K2
A8
J3
A9
K8
A10
AP
J2
A11
H2
A12
Pin
Type
Buffer
Type
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
Function
Clock Signal
Complementary Clock Signal
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
Address Bus 12:0
TABLE 6
Ball Configuration
Rev. 1.2, 2007-04
9
04112007-FHBX-O8HD