HYB25DC512800B Datasheet, PDF (6/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
2
Configuration
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
This chapter contains the chip configuration.
2.1
Configuration of PG-TSOPII-66
The ball configuration of a DDR SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column are
explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1.
Ball#/Pin#
Name
Clock Signals
45
CK
46
CK
44
CKE
Control Signals
23
RAS
22
CAS
21
WE
24
CS
Address Signals
26
BA0
27
BA1
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10
AP
41
A11
Pin
Type
Buffer
Type
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
Function
Clock Signal
Complementary Clock Signal
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
Address Bus 11:0
TABLE 3
Ball Configuration
Rev. 1.2, 2007-04
6
04112007-FHBX-O8HD