HYB25DC512800B Datasheet, PDF (14/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
3
Functional Description
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Field Bits Type¹⁾ Description
TABLE 9
Mode Register Definition
BL
[2:0] W
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
BT
3
CL
[6:4]
001_B 2
010_B 4
011_B 8
Burst Type
See Table 10 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
MODE [12:7]
010_B 2
011_B 3
110_B 2.5
101_B 1.5
Note: CL = 1.5 for DDR200 components only
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 1.2, 2007-04
14
04112007-FHBX-O8HD