HYB25DC512800B Datasheet, PDF (16/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
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02'(
 '6 '//
UHJDGGU
Z
ZZZ
03%7
Field
Bits
DLL
0
Type¹⁾
w
DS
1
MODE
[12:3]
1) w = write only register bit
Description
DLL Status
0_B Enabled
1_B Disabled
Drive Strength
0_B Normal
1_B Weak
Operating Mode
00000000000_BNormal Operation
TABLE 11
Extended Mode Register
Notes
1. A2 must be 0 to provide compatibility with early DDR devices
2. All other bit combinations are RESERVED.
TABLE 12
Truth Table 1a: Commands
Name (Function)
CS RAS CAS WE Address MNE Note
Deselect (NOP)
H X X XX
NOP
1)2)
No Operation (NOP)
L H H HX
NOP
1)2)
Active (Select Bank And Activate Row)
LL
H
H Bank/Row ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
LH L
H Bank/Col Read ¹⁾⁴⁾
Write (Select Bank And Column, And Start Write Burst)
LH L
L Bank/Col Write
1)4)
Burst Terminate
L H H LX
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
LL
H
L Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
LL
L
HX
AR/SR ¹⁾⁷⁾⁸⁾
Mode Register Set
LL
L
L Op-Code MRS
1)9)
1) CKE is HIGH for all commands shown exceptSelf Refresh.V_REF must be maintained during Self Refresh operation.
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-A9 (x16 device); A0 - A9, A11 (x8 device)provide column address ; A10 HIGH enables the Auto
Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
Rev. 1.2, 2007-04
16
04112007-FHBX-O8HD